The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device such as a data processing device (microprocessor) having a high-speed CMOS (complementary metal-oxide-semiconductor) TLB (translation look-aside buffer).
The virtual storage method is a known method of memory management for use with microprocessors.
To use the virtual storage method requires establishing correspondence between two kinds of address space: virtual (i.e., logical) address (called VA) space, and real (i.e., physical) address space.
The most common technique by which to have virtual address space correspond with real address space is what is known as the paging system or page segmenting system. The system involves allocating address space in units of pages.
The paging or page segmenting system involves dividing virtual and real address space into contiguous blocks called pages. The virtual (logical) page numbers (VPN) of virtual address space are arranged to match the real (physical) page numbers (PPN) of real address spaces That is, a virtual address is assigned to the real addresses for each of the pages.
Suppose that a virtual address space accessed by a 32-bit virtual address (VA 31 : 0!) is divided into 4-kilobyte (KB) pages. In such a case, the high-order 20 bits of the virtual address (VA 31 : 12!) are used to designate the page number of a page in the virtual address space. The low-order 12 bits (VA 11 : 0!) of the virtual address are used to specify a displacement (or offset) address within the page.
In the description that follows, the notation m : n! is assumed to indicate the bit positions from bit m to bit n.
A page number in the virtual address space is translated into the corresponding page number in the real address space (the process is called address translation or memory mapping). A page number in the real address space is combined with a replacement address for access to real memory.
It should be noted that the replacement address in each page is not translated.
Translation of a page number in the virtual address space to the corresponding page number in the real address space is carried out by both hardware and software: by a memory management unit (called the MMU), and by the operating system.
High-performance microprocessors generally incorporate a memory with functions for address translation called a translation look-aside buffer (TLB) in order to implement a high-speed virtual storage setup.
The TLB, included in the MMU, translates a given page number of the virtual address space into the corresponding page number of the real address space.
The translation table as a whole for designating correspondence between the page numbers in the virtual address space and those in the real address space (real memory) is held in a page table in main memory or in a secondary storage (memory) device.
A partial copy of the page table is retained in the TLB. The TLB works as a cache memory (address mapping cache memory) for the page table.
The address translation time of the TLB affects the speed of processing by the microprocessor in question. Thus attempts have been made to shorten the address translation time of the TLB.
Part of such attempts are presented illustratively as TLB circuits disclosed in the following two publications for reference:
(A) T. Takayanagi et al., "2.6 Gbyte/sec Bandwidth Cache/TLB Macro for High-Performance RISC Processor" Proceedings of Custom Integrated Circuits Conference, pp. 10.2.1-10.2.4, 1991
(B) G. Gerosa et al., "A 2.2W, 80 MHz Superscalar RISC Microprocessor," J. Solid-State Circuits, Vol. 29, No. 12, pp. 1440-1454, Dec. 1994
The TLB circuit discussed in the reference (A) above takes a total of 12 ns for address translation and cache memory access. The TLB has a match line discharge circuit implemented as a dynamic circuit so as to shorten the address translation time.
The TLB circuit described in the reference (B) attempts to shorten the address translation time by having its comparator arrangement operating as a dynamic circuit.
The virtual storage setup (paging or page segmenting system) operating in units of pages requires as many "address translation pairs" as the number of pages involved.
An address translation pair is a page number of virtual address space paired with the corresponding page number of real address space. These pairs are held in the page table to designate the correspondence between the two kinds of address space.
When the memory space of a fixed storage capacity is divided into pages, the smaller the size of each page (i.e., page size), the larger the number of pages available in the divided memory space.
Conversely, the larger the page size, the smaller the number of pages divided and made available. Larger page sizes mean a smaller number of address translation pairs, which translates into a less memory capacity required for the page table.
However, making the page size too large can increase unusable fields within the pages (due to internal fragmentation). For that reason, high-performance microprocessors recently marketed generally allow any of a plurality of page sizes to be selected for different purposes.
To handle a plurality of page sizes requires that the TLB also accommodate a plurality of page sizes.
In addition to the address translation time and the number of usable page sizes, the so-called hit rate is cited as an important performance indicator of the TLB (the hit rate is a rate at which necessary address translation pairs are found in the TLB).
The hit rate is related to what kind of associative method is in use and how large the size of the TLB is (i.e., the number of entries).
There are two kinds of associative methods CAM (content addressable memory) method, and set-associative method.
The CAM method permits a high hit rate with the use of a small-capacity memory. One disadvantage of this method is that it is difficult to design. Another disadvantage is the tendency of a setup implementing the CAM method to consume large amounts of power. That is, the CAM-based setup has its numerous memory cells incorporate a comparator each, the large number of comparators being liable to dissipate high quantities of power in operation.
On the other hand, although the set-associative method provides a high hit rate only in combination with a large-capacity memory, it nevertheless offers a number of advantages. One such advantage is a low level of power consumption where the degree of association (i.e., number of ways) is low. Another advantage is that a setup implementing the set-associative method is relatively easy to design. Moreover, since most cache memories operate on the set-associative methods the same kind of memory as cache memories may be adopted by the TLB. This reduces the design period of the TLB circuit.
The following publications illustratively disclose a page size variable TLB each:
(C) Tanaka et al., "5-ns Access Time CMOS Translation Look-aside Buffer," technical report of the Institute of Electronics, Information and Communication Engineers of Japan, ICD92-57, pp. 29-35, 1992
(D) Japanese Patent Laid-Open No. Hei 5-282877
The page size variable TLB circuits disclosed in the references (C) and (D) above use a CAM circuit to vary the range of comparison (associative range) between an input virtual address (i.e., its tag field) and the (tag) data held in memory. The associative range is varied in accordance with the memory cell data indicating page sizes. The scheme permits storage of address translation pairs of different page sizes for each of the entries accommodated.
Another page size variable TLB circuit is disclosed illustratively by the following publication:
(E) T. Takayanagi et al., "Embedded Memory Design for a Four Issue Superscalar RISC Processor," Proceedings of Custom Integrated Circuits Conference, pp. 26.1.1-126.1.6, June 1994
The page size variable TLB circuit disclosed in the reference (E) above constitutes a TLB setup that utilizes the set-associative method in varying, according to the page size in effect, those bit positions of a given virtual address which are handled by control signals as an index field in part (an address part for selecting a set-associative set in the virtual address) and as a tag field in another part (an address part of the virtual address for comparison with the data held in the TLB).